The present invention relates to the configuration of a semiconductor device to improve the reliability of the interconnection wiring formed on the surface of the device. In particular, the present invention relates to the configuration of a wiring layer to provide good step coverage for contact holes formed in an insulation layer through which the wiring layer contacts the device electrodes.
In recent semiconductor devices, especially in integrated circuits (ICs), the dimension of the devices fabricated on a chip has become very small, however the insulation layer covering the surface of the device cannot be made as thin. Thus, the openings of contact holes formed in the insulation layer through which the wiring layer contacts to the electrodes of the devices is very small. The small openings increases the difficulty of making contact between the wiring layer formed on the surface of the insulation layer with the electrode positioned on the bottom of the contact holes. The wiring layer must cover the side walls of the contact holes of the insulator, but this becomes difficult when the opening of the contact hole becomes comparative in size to the depth of the contact hole.
To cover a side wall of a stepped portion with wiring material is called in the art, step covering or step coverage. Usually aluminum is sputtered to form the wiring layer over the insulated surface of the device The step coverage of sputtered aluminum is poor, so the wiring pattern often breaks and causes disconnection at the stepped portion on the surface of the device on which the wiring layer is formed thus causing malfunctioning of the device. In order to overcome this problem, the sputtering is done from various directions so that the side wall of the stepped portion is covered by the wiring material.
As mentioned before, when the device size decreases, and the opening of the contact hole becomes comparative to the depth of the hole, the side sputtering becomes ineffective. Such situations are shown in FIG. 1, which schematically illustrates the cross section of a device at a portion close to a contact hole. In the figure, an n type silicon substrate 31 and an n.sup.+ type contact region 32 are to be contacted by the wiring layer. 32 may be a contact region for the device (not shown completely), and 33 is a surface coating insulation layer such as a silicon dioxide (SiO.sub.2) layer for example. A contact hole 35 is formed in the insulation layer 33 through which the wiring layer 34 contacts with the contact region 32. The wiring layer 34 is composed of aluminum sputtered on the insulation layer 33. The sputtering is done vertically and also from slanted directions in the figure. However, as can be seen, the thickness of the aluminum layer on the side walls of the contact wall is thin at the side walls of the contact hole 35. Namely, the step coverage of sputtered aluminum is poor, and it often causes disconnection of the wiring layer.
There is another problem in the aluminum wiring layer. Aluminum is likely to form an eutectic alloy with silicon, and it forms spikes which penetrate through the contact region 32 and causes a short circuit between the wiring layer 34 and the substrate 31. Several solutions have been proposed to overcome such problems.
One proposal is to provide a thin layer (approximately 500 .ANG.) of polycrystalline silicon (not shown) between the aluminum layer 34 and the n.sup.+ contact region 32. In this method, the resistivity of the silicon layer can not be substantially reduced, so recently an alloy of aluminum and silicon, tungsten or titanium is sputtered. This method is disclosed in, for example, French Pat. No. 8409313 by Joel Alman, June 14, 1984 (the same application has been published as Japanese Laid Open Pat. No. 61-10256, Jan. 17, 1986). But in this method, the problem of step coverage of the sputtered material still remains.
Another proposal is to bury the contact holes with conductive material such as polysilicon (polycrystalline silicon). In this case, the polysilicon must be doped with p or n type materials in accordance with the conductivity type of the contact regions beneath the polysilicon in order to make a good ohmic contact. If the conductivity type of the contact regions in the chip all have the same conductivity type, the doping can be done in a process to grow the polysilicon layer (chemical vapor deposition for example) But usually, the chip contains both p and n type contact regions, so the doping must be done selectively in accordance with the conductivity type of the contact regions beneath the polysilicon. Such selective doping must be done by diffusion process from the surface of the grown polysilicon layer. However, the conductivity of the diffused layer becomes low as the distance from the surface becomes large. Therefore, the resistivity of the buried material in the contact holes becomes high, and the resistance of the wiring layer increases. Accordingly, though this method has been proposed, its adoption in practical use was very rare.
The conductivity of the wiring layer is of increasing importance for a device which is operated at high speed or for large scale integrated circuits in order to decrease heat dissipation.